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Description
• Collaborate with system architects, analog designers, and digital teams to establish precise model specifications for mixed-signal IPs.• Develop high-speed models from schematics and design specs.• Build mixed-signal testbenches and integrate models into projects to close the simulation loop.• Develop verification plans, run regression suites, and debug digital/analog corner cases.• Correlate model accuracy and performance against transistor-level SPICE simulations.• Drive modeling methodologies to accelerate simulation turnaround times and ensure tapeout readiness.
Minimum Qualifications
Minimum requirement of a bachelors degree
Preferred Qualifications
Experience developing digital logic or behavioral models for analog and mixed-signal circuits (e.g., SystemVerilog, Real Number Modeling / RNM, or Verilog-A/AMS).Solid fundamentals in digital design and RTL development (SystemVerilog/Verilog).Good knowledge of analog circuits and architectures (e.g., power converters, regulators, references, ADCs/DACs).Experience with industry-standard simulation and verification tools (e.g., Xcelium, Virtuoso).Strong debugging and cross-functional communication skills.
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