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Description
APPLE INC has the following available in Beaverton, Oregon. Collaborating with all disciplines (vertical product model). Ensuring the quality of the SOC or an IP or subsystem. Reviewing design and architecture specifications and working closely with design & micro-architecture teams. Understanding the functional and performance goals of the design and use this knowledge to test effectively. Developing test plans, tests & coverage plans as well as define Apple’s next generation verification methodology & test benches. Communicating and collaborating with design, architecture and software to understand the use cases and corner conditions and driving test cases. Running and triaging regressions, tracking bugs, and analyzing coverage to achieve top results. 40 hours/week.
Minimum Qualifications
Master’s Degree or foreign equivalent in Computer Engineering, Electrical Engineering or related field.Experience and/or education must include:Utilizing System Verilog and UVM framework to write test bench codeCreating test plans using constrained random verification (CRV) or directed testing to verify ASICsUtilizing C to write microprocessor tests for ASIC/Embedded tests.Reviewing design and architecture specifications and working closely with design and micro-architecture teams to understand functional and performance goalsDeveloping test coverage plan, collecting test bench coverage, and resolving coverage gaps in ASIC test suiteImplementing IP block test environments and test cases for ASICsUtilizing Xcelium, Questa, or VCS to analyze simulation failuresProgramming scripts in Python or Perl to automate test bench analysis
Preferred Qualifications
N/A
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