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Junior FPGA Engineer

Eagle Seven
Posted 2 months ago, valid for 13 days
Location

Chicago, IL, US

Salary

$150,000 per year

Contract type

Full Time

Paid Time Off
Life Insurance
Disability Insurance
Flexible Spending Account

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Sonic Summary

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  • Eagle Seven is looking for a Junior FPGA Design / Verification Engineer to join their engineering team focused on developing HDL solutions for electronic trading systems.
  • The position requires 1-3 years of relevant experience, with a preference for candidates with academic or internship experience in PCIe, Ethernet, or memory interfaces.
  • Key responsibilities include writing SystemVerilog code, developing testbenches using ModelSim, and automating validation processes with Python.
  • The minimum base salary for this role starts at $150,000, and the position is eligible for a discretionary performance bonus.
  • Eagle Seven offers a comprehensive benefits package including medical, dental, and vision coverage, as well as a 401k plan with employer match.

Eagle Seven is seeking a Junior FPGA Design / Verification Engineer to become an integral member of the engineering team dedicated to the development of HDL solutions for our high frequency, low latency electronic trading systems. The role will be a part of the hardware development team and will work alongside senior engineers to design, simulate, and validate high-performance hardware modules. This is a hands-on role where the candidate will focus on building robust testbenches, running functional simulations, and automating validation suites to ensure our trading systems remain deterministic while providing ultra-low latency.

 

Primary Responsibilities include: 

  • Assisting in writing and maintaining clean, synthesizable SystemVerilog code for new features within our FPGA-based trading platform
  • Developing comprehensive testbenches using ModelSim to verify logic blocks and ensuring functional coverage before hardware deployment
  • Utilizing Python to create automated test scripts and data-processing tools that validate hardware outputs against expected trading model behavior
  • Supporting production deployments by capturing and analyzing various real-time data to identify design faults, edge cases, or timing issues
  • Maintaining clear design documentation and test results for all assigned modules

Skills & Experience:

  •  Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science or other related disciplines
  • 1-3 years of relevant experience; academic or internship experience with PCIe, Ethernet, or memory interfaces (DDR) preferred
  • Strong foundational knowledge of SystemVerilog (or Verilog) for design and verification
  • Hands-on experience with ModelSim (or similar tools like Questa, Vivado Simulator) for simulation, debugging, and waveform analysis
  • Proficiency in Python for automation, data analysis, and interacting with APIs
  • Solid understanding of synchronous design, state machines, clock domains, and FIFO structures
  • Familiarity with FPGA vendor flows (Xilinx/AMD Vivado or Intel/Altera Quartus) preferred
  • Demonstrated interest in finance, trading, and/or low-latency systems preferred 

Eagle Seven offers a competitive and comprehensive benefits package to all full-time employees.

  • Medical PPO and HMO coverage through BlueCross BlueShield
  • Health Savings Account (with enrollment into a High Deductible Health Plan)
  • Dental coverage through Guardian
  • Vision coverage through VSP
  • 401k Retirement Savings Plan with Employer Match
  • Company Paid Life Insurance
  • Company Paid Disability Insurance
  • Paid Time Off
  • Flexible Spending Account
  • Pre-tax Transit Benefits
  • Complimentary Lunch and Beverages

The minimum base salary for this role starts at $150,000. This role is eligible for a discretionary performance bonus as part of the total compensation package, in addition to the benefits listed above. Exact compensation offered may vary based on factors including, but not limited to, the candidate's experience, qualifications, and skill set.




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