Photolithography Process Development Engineer (Advanced Patterning)

Change the world. Love your job. 

We’re at the forefront of an exciting era of semiconductor innovation at Texas Instruments’ LFAB in Lehi, Utah — home to our state-of-the-art 300mm manufacturing facility now ramping our most advanced 28nm analog and embedded process technology in the heart of the Silicon Slopes. As part of our Advanced Technology Development (ATD) organization, you will be challenged with developing and characterizing the next generation node.  We are seeking a highly skilled and hands-on Process Development Engineer with deep expertise in advanced-node semiconductor manufacturing. This role focuses on the next generation 20nm-class logic technologies, with primary responsibility for photolithography and litho-etch integration, including advanced patterning techniques such as pitch doubling (SADP/LELE).  This role will also work directly with the Resolution Enhancement Techniques (RET) team to create Optical Proximity Corrections (OPC) and validate final pattern meets design tolerance.  

You will play a critical role in developing, optimizing, and scaling patterning processes to meet aggressive performance, yield, and manufacturability targets. This is a high-impact position working at the intersection of lithography, materials science, and plasma etch.  

Responsibilities include:

• Modeling & Simulation: Utilize lithography simulation software (e.g., Prolith, S-Litho) to analyze process windows and optimize patterning results.
• Metrology & Yield Improvement: Utilize advanced metrology (CD-SEM, Overlay, Scatterometry) to identify defects and improve Critical Dimension Uniformity (CDU) and overlay performance.
• Vendor & Subsystem Interaction: Work with equipment vendors to evaluate new materials, photoresists, and tool hardware upgrades.
• Data Analysis & SPC: Analyze process data, identify root cause, and implement robust process improvements.  Apply Statistical Process Control (SPC) and Design of Experiments (DOE) to develop new processes to enable Litho shrink processes. 
• Pathfinding & Technology Transfer: Define pathfinding activities for new patterning technology, evaluating High NA Immersion for next-generation nodes. Lead technology transfer from R&D to HVM for photolithography processes.
• Photo Process Characterization: Lead development to create next generation Litho Shrink processes for 20nm class logic nodes.
  • Drive litho-etch integration (LE, LELE, SADP / pitch doubling) for advanced patterning schemes.
  • Develop and implement resolution enhancement techniques (RET) and optical proximity correction (OPC)strategies.
  • Evaluate and select materials systems, including photoresists, hard masks, and anti-reflective coatings.
  • Characterize and reduce patterning defects, including line edge roughness (LER), CD variation, and overlay errors.
  • Collaborate closely with Etch team to optimize pattern transfer, profile control, and CD uniformity Interface with cross-functional teams including design, integration, yield, and manufacturing.