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Sr. Mixed Signal Design Verification Manager

Qorvo
Posted 3 months ago, valid for 11 days
Location

Richardson, TX 75081, US

Salary

Competitive

Contract type

Full Time

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Sonic Summary

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  • Qorvo is seeking a Top-level Design Verification Engineer for its Power Management division, which focuses on innovative solutions for various applications including mobile and industrial sectors.
  • The role requires a Master's degree in Electrical Engineering or a related field and at least 13 years of experience in AMS design or verification of analog and power-management ICs.
  • Responsibilities include managing a team of verification engineers, driving technical strategy, and developing design verification plans aligned with customer use-cases.
  • Candidates should possess strong technical skills in UVM and mixed-signal concepts, along with effective communication and collaboration abilities.
  • The position may require occasional travel and offers a competitive salary, though specific figures are not disclosed in the job description.

Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems-level expertise and global manufacturing scale to quickly solve our customers' most complex technical challenges. Qorvo serves multiple high-growth segments of large global markets, including consumer electronics, smart home/IoT, automotive, EVs, battery-powered appliances, network infrastructure, healthcare and aerospace/defense. Visit www.qorvo.com to learn how our innovative team is helping connect, protect and power our planet.

 

Qorvo’s fast-growing Power Management division, focused on Power loss protection, PMICs, Motor Control, and Battery Management solutions for a wide range of Mobile, Consumer, IOT and Industrial applications, is looking for an experienced Top-level Design Verification Engineer to create next generation and world-class designs in power management solutions.

Responsibilities: 

  • Manage and grow a team of verification engineers with different levels of experience, from entry level to senior principal level.
  • Drive technical direction and strategy for verification excellence.
  • Serve as customer-facing for catalog and custom power-management ICs including motor driver, power-loss protection, point of load, and battery management IC solutions.
  • Develop and execute metric-driven design verification plans based upon IC functional, performance, and test specifications, with a strong focus on the customer use-case.
  • Develop constrained random tests and automated checkers within our TLDV UVM environment.
  • Build high performance, accurate RNM, or VerilogAMS models to support TL simulation.
  • Collaborate with design team to resolve issues identified during verification.
  • Partner with internal design and test teams to ensure device first-pass testability.
  • Continuously improve and align verification methodologies with industry best practices.
  • Automate verification tasks where applicable.

 

Required Qualifications: 

  • Bachelor’s degree in electrical engineering or a related field, with strong focus on mixed-signal circuit design and verification.
  • 15+ years of experience or an equivalent amount of advanced education and experience in AMS design or verification of analog and power-management ICs.
  • Experience managing or being a functional team lead.
  • Strong technical background with hands-on experience in UVM, analog and digital design fundamental, and system level knowledge of power management ICs.
  • Excellent problem-solving and debugging skills
  • Effective communication and collaboration skills.
  • Expertise in mixed-signal concepts such as Spice/Spectre and event-based simulator, co-simulation environment, simulation debug, silicon debug

 

Preferred Qualifications: 

  • Master’s degree in electrical engineering or a related field, with strong focus on mixed-signal circuit design and verification.
  • Experience in Top-Down Design Methodology.
  • Proficiency in shell or Python scripting.
  • Familiarity with SV-UDN/EENET modeling techniques.
  • Experience with both GUI and command-line simulation flows.
  • Proficiency with SV Assertions and Functional coverage.
  • Understanding integration of AI into a verification workflow

 

Other: 10% or less domestic or international travel may be required

 

#LI-NN1 

MAKE A DIFFERENCE AT QORVO   

 We are Qorvo. We do more than create innovative RF and Power solutions for the mobile, defense and infrastructure markets – we are a place to innovate and shape the future of wireless communications. It starts with our employees. As a unified global team, we bring a commitment to excellence, growth and a passion for creating what's next. Explore the possibilities with us.

We are an Equal Employment Opportunity (EEO) employer and welcome all qualified applicants. Applicants will receive fair and impartial consideration without regard to any characteristics protected by applicable law, including race, color, religion, sex (as defined by law), national origin, age, military or veteran status, genetic information, or disability. 




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