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RTL / Circuit IP Design Engineer

Advanced Micro Devices, Inc
Posted 3 months ago, valid for 10 days
Location

San Jose, CA, US

Salary

Competitive

Contract type

Full Time

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Sonic Summary

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  • AMD is seeking a candidate to plan, build, and execute the implementation of features for their programmable embedded IP, focusing on power, performance, and area targets.
  • The ideal candidate should have a Bachelor's or Master's degree in computer engineering or electrical engineering and possess proficiency in IP level RTL implementation and debugging RTL code.
  • Candidates must have experience working collaboratively with engineers across different sites and time zones, as well as strong analytical and problem-solving skills.
  • The role requires a minimum of 5 years of relevant experience and offers a competitive salary, although the exact figure is not specified in the job description.
  • AMD values innovation and collaboration, emphasizing a culture that encourages diverse perspectives and career advancement.


WHAT YOU DO AT AMD CHANGES EVERYTHINGĀ 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Ā Together, we advance your career.Ā Ā 




THE ROLE:Ā 

The focus of this role is to plan, build, and execute the implementation of new and existing features for AMD’s programmable embedded IP, resulting in final designs that meet product defined power, performance, and area targets with intended functionality that operates on silicon and is modeled accurately for customer design use .   

  

THE PERSON:  

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.Ā 

  

KEY RESPONSIBILITIES:  

  • Collaborate with architects, hardware engineers, and software engineers to understand the new features to be implemented
  • Author implementation documentation, accounting for interactions with other features, the hardware, and the software modeling use casesĀ 
  • Estimate the time required to implement the new features, collaborate with design verification test development, and any execute required changes based on cross functional feedbackĀ 
  • Build the directed and random verification testsĀ 
  • Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues  
  • Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirementsĀ 

  

PREFERRED EXPERIENCE:  

  • Proficient in IP level RTL implementationĀ 
  • Proficient in debugging RTL code using simulation tools  
  • Proficient in navigating UVM generated test results and working in Linux and Windows environmentsĀ 
  • Experienced with Verilog and System Verilog 
  • Strong understanding of circuit design concepts, translating circuit designs in an optimal way to either custom implementations or with best practices for RTL synthesis  
  • Automating workflows in a distributed compute environment.   
  • Proficient in analytical problem solving, specifically with troubleshooting component designs (e.g., timing analysis, constraint setting)
  • Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/processĀ 
  • Strong background in developing and verifying SAPR constraintsĀ 
  • Good understanding and hands-on experience in UPF conceptsĀ 
  • Good working knowledge of clocking, reset, and power domain crossingsĀ with some related experience.   
  • Scripting language experience: Python, Perl, Ruby, Makefile, shell preferred.   
  • Exposure to leadership or mentorship is an assetĀ 
  • Experience with circuit macro generation, characterization, and collateral release processes
  • Desirable assets with prior exposure to high speed interfaces    

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ACADEMIC CREDENTIALS:  

  • Bachelors or Masters degree in computer engineering/Electrical EngineeringĀ 

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This role is not eligible for visa sponsorship.

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#LI-CJ3

#LI-Hybrid

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Benefits offered are described:Ā  AMD benefits at a glance.

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AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.Ā Ā  We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

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AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.Ā  AMD’s ā€œResponsible AI Policyā€ is available here.

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This posting is for an existing vacancy.




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