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Digital Physical Design Engineer – STA / Timing Analysis –  Semiconductors - Hybrid. Exciting Semiconductor Company seeks a STA / Timing Engineer to join their talented team, bringing 5+ years’ experience of RTL to GDS implementation flow, expertise in Timing /SDC constraints as well as good scripting capabilities.
The role will involve: Working closely with the Architecture and RTL team to ensure right-first-time high volume silicon production. You’ll undertake Timing Constraints development and validation, sign-off Static Timing Analysis and support for full chip and block level timing closure as well as supporting IP and chip level integration.
Skills and Experience required includes:
- Bachelors / Masters Degree in Electronics, Computer Science or similar.
- 5+ year’s experience working in Digital Physical Design role.
- Expertise in Timing / SDC constraints generation.
- Good knowledge of RTL to GDS implementation flow (synthesis, P&R, LEC, STA).
- Modern semiconductor process technologies such as 28nm, 22nm, 16nm, 7nm, 3nm.
- Proven Scripting skills (Python, shell or TCL, make).
- Familiarity with EDA tools for design and verification such as Cadence Tempus.
This Digital Physical Design Engineer (STA / Timing) role can be based in Northants or at the company offices in Germany or Switzerland. A highly competitive salary package will be offered, with Hybrid working and generous shares.
