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Lead Solutions Engineer – Runset Enablement (Physical Verification)

Cadence Design Systems
Posted 2 months ago, valid for 18 days
Location

Austin, TX 78714, US

Salary

$80,000 - $96,000 per year

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Contract type

Full Time

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Sonic Summary

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  • Cadence is looking for a Lead Solutions Engineer specializing in runset enablement to support advanced semiconductor technologies.
  • The position requires a Master's degree with at least 5 years of experience or a PhD with 3 years in Electrical Engineering, Computer Science, or a related field.
  • Key responsibilities include leading the development and validation of Pegasus DRC and LVS runsets, as well as collaborating with R&D for product improvements.
  • Candidates should have proven expertise in developing and validating runsets for Pegasus or similar tools, along with proficiency in scripting languages and Linux/Unix environments.
  • This role offers a competitive salary and emphasizes leadership, mentoring, and collaboration within cross-functional teams.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We are seeking a Lead Solutions Engineer specializing in runset enablement to support advanced semiconductor technologies. This role is critical for timely delivery of physical verification solutions by providing full-time coverage in the U.S. time zone. You will lead development and validation of Pegasus DRC and LVS runsets, collaborate with R&D on CCRs, and enable customer adoption through robust automation and best practices.

Key Responsibilities

  • Lead development and validation of Pegasus DRC and LVS runsets for advanced nodes.

  • Architect automation frameworks for regression execution, issue detection, and validation reporting.

  • Collaborate with R&D to resolve CCRs, influence product roadmap, and implement performance improvements.

  • Provide technical enablement and support for customers on tool usage and advanced methodologies.

  • Mentor junior engineers and establish best practices for runset development and QA.

  • Work closely with internal teams to ensure timely delivery of verification solutions.

Qualifications

  • MS degree with 5+ years of experience or PhD with 3+ years in Electrical Engineering, Computer Science, or related field.

  • Strong understanding of semiconductor design and physical verification flows.

Experience and Technical Skills

  • Proven expertise in developing and validating DRC and LVS runsets for Pegasus or similar tools (Calibre, ICV, Assura).

  • Good-to-have: Experience with PERC and Fill runsets.

  • Deep knowledge of advanced process technologies and methodologies (Ground Rules, SmartFill, ESD).

  • Proficiency in scripting languages (TCL, Python, Perl) and Linux/Unix environments.

  • Familiarity with chip fabrication processes and multi-die integration challenges.

  • Experience in automation frameworks for regression and validation.

Behavioral Skills

  • Strong leadership and mentoring capabilities.

  • Excellent written, verbal, and presentation skills.

  • Ability to influence cross-functional teams and drive strategic initiatives.

  • Innovative mindset to explore unconventional solutions and optimize workflows.

  • Operate with integrity and foster collaboration across global teams.

Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.

We’re doing work that matters. Help us solve what others can’t.




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