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At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.

AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.

The Role:

AMD's NBIO (Northbridge I/O) organization is seeking an experienced ASIC Formal Verification Architect to join the IOHUB team. This team develops industry-leading I/O connectivity, virtualization, and infrastructure technologies that power next-generation data center, AI/ML, client, graphics, embedded, and semi-custom products.

As an ASIC Formal Verification Architect, you will play a critical role in defining and executing formal verification strategies for complex IP and SoC designs. Working closely with architects, designers, and verification teams, you will drive verification planning, methodology development, infrastructure architecture, and sign-off activities while leading a team of engineers to deliver high-quality silicon solutions.

This position offers the opportunity to influence verification methodology across multiple projects, mentor engineers, and help shape the future of AMD's formal verification capabilities.

The Person:

The ideal candidate is a technical leader with deep expertise in formal verification methodologies and a passion for solving complex design and verification challenges. You thrive in a collaborative, fast-paced environment and can effectively drive projects from concept through verification closure.

You possess:

Strong analytical and problem-solving skills with exceptional attention to detail
Proven leadership experience guiding technical teams and mentoring engineers
Excellent communication, collaboration, and interpersonal skills
Self-motivation with the ability to independently drive initiatives to completion
A continuous improvement mindset and passion for technical innovation
The ability to balance multiple priorities in a dynamic, fast-paced environment

Key Responsibilities:

Lead and mentor a team of formal verification engineers across multiple IP and SoC projects
Define and drive formal verification architecture, methodologies, and development plans in partnership with IP architects and design teams
Develop comprehensive formal verification test plans and execute verification closure strategies
Architect, develop, and maintain reusable formal verification environments, properties, components, and infrastructure
Drive adoption of industry-leading formal verification methodologies and best practices across the organization
Perform formal connectivity verification, deadlock/livelock analysis, and protocol verification for complex I/O and arbitration-intensive designs
Apply advanced formal techniques, including abstraction, decomposition, and assume-guarantee methodologies, to solve challenging verification problems
Debug and triage failures identified through formal verification tools and root-cause complex design issues
Collaborate closely with design, validation, and post-silicon teams to reproduce and resolve functional issues
Contribute to verification sign-off activities and ensure delivery of high-quality silicon solutions
Foster technical excellence through coaching, mentorship, and knowledge sharing across the team

Preferred Experience:

Strong understanding of digital design and computer architecture
Verification skills: Formal verification (Static and Dynamic), Assertion based verification, FPV and DPV
Experience with CDC and RDC formal verification methodologies; proficiency with JasperGold CDC/RDC and Connectivity apps strongly preferred
Experience with sequential/logical equivalence checking (SEC/LEC)
Ability to apply abstraction, decomposition, and assume-guarantee reasoning to tackle intractable formal problems at scale
Strong Design debug, Deep bug hunting skills
Formal test planning, Formal tools – Jasper, VC-formal.
Design knowledge of CPU, GPU, Bus/Noc/Interconnect, Memory Controllers, Cache preferred
Familiarity with UVM-based simulation environments and experience bridging formal and simulation-based verification flows
System Verilog, Verilog or VHDL, Scripting skills are an asset.

Academic Credentials:

BS/MS degree in Engineering (Electrical, Electronics, Computer) or Computer Science.

This role is not eligible for visa sponsorship.

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

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