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Description
In this role you will: - Interact with RTL, architecture teams to understand physical design constraints related to timing and be the central point of contact to provide these to backend design flows. - Work with Synthesis and Physical Design teams to implement the best design optimized for power, performance and timing. - Setting up all DFT modes and making sure all test features are properly timed. - Assemble the top level design for STA ensuring accurate analysis by reviewing all the logs and reports. - Create and maintain scripts and automation to ensure high quality STA reports and work with other teams for timing closure. - Run ECO flows on the design and responsible for close timing. - Drive and support tapeout activities by running a full suite of signoff checks to ensure a high quality silicon for manufacture. - Work with CAD and Vendors to constantly improve the flow and bring in groundbreaking features to the analysis flows.
Minimum Qualifications
Bachelors degree in Computer Science or Computer Engineering + 3 years relevant experience. Experience in STA and timing closure or physical design. Experience with scripting languages such as TCL, Python, Perl, shell scripting etc.
Preferred Qualifications
Masters degree preferred. Experience working with EDA tools and exposure to their APIs. Familiar with STA concepts and good understanding of cross-talk, OCV, noise, etc. Experience in analysis of large volume data, identifying and driving timing fixes, generate ECOs etc. Willingness to work with multiple teams like synthesis, physical design, DFT, CAD and drive timing fixes and influence timing closure. Good understanding in one or more multi-functional areas like DFT, synthesis, PD, clocking and the interaction of these domains to STA. Able to identify critical items for timing closure and drive solutions.
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