Description
Deliver high quality design collateral, including RTL, to Physical Design teams Assess and integrate IP from other Apple teams Close timing, power, area, and lint for design by optimizing RTL and constraints Drive performance, power, area, and functional goals Provide schedules to IP teams and management Collaborate effectively with IP teams spanning multiple sites
Minimum Qualifications
BS/MS CE or EE Experience in one or more of the following areas: logic optimization, synthesis, timing analysis, floor-planning, power intent descriptions, and clock domain clock crossings Experience writing RTL in Verilog and/or System Verilog Experience with logic simulation and debug
Preferred Qualifications
Ability to write one or more scripting languages Experience in Graphics hardware design Experience in power management for large designs like CPUs, GPUs, or SOCs
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