Job Details:

Job Description:

About Altera

At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

About the Role

Altera is seeking an experienced Security Architect to define and drive the security architecture for next-generation FPGA, SoC, and ASIC products. This highly visible technical leadership role will be responsible for shaping long-term security strategy, influencing product architecture, and leading the design and deployment of advanced hardware security technologies across multiple product generations.

As a senior technical leader, you will partner closely with architecture, silicon design, firmware, software, validation, DFT, product security, and executive leadership to establish security direction, define architectural roadmaps, and ensure our products deliver industry-leading security, resilience, and compliance. This role requires deep expertise in silicon security, Root of Trust (RoT), secure boot, hardware cryptography, secure provisioning, threat modeling, post-silicon validation, and secure debug architectures.

Salary Range

The pay range below is for the United States market. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$189,300 - $260,000 USD

We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.

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Qualifications:

Minimum Qualifications

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field and 15+ years of experience in semiconductor architecture, hardware security, silicon design, or related engineering disciplines.
10+ years of experience developing security validation methodologies, hardware verification strategies, or post-silicon validation solutions.
8+ years of experience working with cryptographic technologies including secure authentication, hardware cryptography, attestation protocols, TPM, SPDM, or related security standards.
8+ years of experience leading complex cross-functional technical initiatives involving architecture, RTL design, firmware, software, validation, product security, and manufacturing teams.
Demonstrated technical leadership with a track record of influencing architecture decisions across multiple engineering organizations and product generations.

Preferred Qualifications

Master's degree in Electrical Engineering, Computer Engineering, Computer Science, Cybersecurity, or related field and 18+ years of industry experience, or Ph.D. with 15+ years of industry experience.
15+ years of experience architecting security solutions for complex FPGA, ASIC, CPU, or SoC products.
10+ years of experience with Root of Trust (RoT), Secure Boot, SPDM, TPM, DICE, Caliptra, platform attestation, or trusted execution technologies.
10+ years of experience with hardware cryptography including AES, RSA, ECC, SHA, PUF, TRNG, post-quantum cryptography, or secure key management.
8+ years of experience leading security certification efforts including FIPS, Common Criteria, or equivalent industry security standards.
8+ years of experience serving as a technical lead or architect responsible for security strategy across multiple product families.
Experience with secure firmware architecture, BootROM development, trusted execution environments, secure manufacturing flows, or Design for Debug (DFD)/Design for Test (DFT).
Strong record of innovation demonstrated through patents, publications, conference presentations, or significant technical contributions to hardware security.

Job Type:

Regular

Shift:

Shift 1 (United States of America)

Primary Location:

Austin, Texas, United States

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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