Senior ASIC Floorplan Design Engineer

NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world’s leading SoC's and GPU's. This position offers a unique opportunity to craft and influence the design and development of the next generation GPU and SoC, impacting product lines ranging from consumer graphics to self-driving cars and AI. Responsibilities include working with architects, design leads, physical design leads, and package leads to develop and optimize floorplans during early chip development; driving the area review process; collaborating with the ASIC design team to identify area, interconnect, and floorplan improvement opportunities; solving timing and routing congestion issues; and building tools to optimize chip area and speed of execution. Requirements include a Masters Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent experience, 6+ years of relevant work experience, deep hardware engineering background in VLSI and/or Computer Architecture, experience in Verilog, System Verilog or similar HVL, experience with CAD and physical design methodologies, strong communication and interpersonal skills, and programming experience in Python, Perl, and C/C++. Experience in driving development of large scale ASIC floorplan is a plus. NVIDIA is an equal opportunity employer committed to diversity.