Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

At Tenstorrent, we build open, state of art compute for real workloads and real developers.

You will own CPU core‑level verification, shaping how our out‑of‑order RISC‑V CPUs behave in silicon.

This role is hybrid, based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

You bring 8+ years in CPU verification or closely related digital design.
You know high‑performance out‑of‑order CPU microarchitecture in depth.
You work comfortably with RTL, waveforms, logs, and complex debug scenarios.
You communicate clearly across design, DV, emulation, and post‑silicon teams.

What We Need

Plan and drive functional verification for CPU core features and microarchitectural scenarios.
Develop UVM, assembly, and C/C++ stimulus for ISA and microarchitectural coverage.
Develop/debug C++ functional models of RISC-V extensions and un-core components such as APIC and IOMMU.
Debug simulation and emulation regressions using waveforms, logs, and RTL understanding.
Build and refine coverage models to track and close architectural and microarchitectural coverage.
Improve core, cluster, and chip‑level testbenches and debug infrastructure.
Support design bring‑up across simulation, emulation, and post‑silicon environments.
Collaborate with design, test, and validation to deliver robust CPU cores and clusters.

What You Will Learn

How Tenstorrent designs and validates high‑performance RISC‑V CPU cores and clusters.
Techniques for spanning pre‑silicon, emulation, and post‑silicon verification with shared stimulus.
Ways to scale coverage, debug, and infrastructure across multiple CPU programs.
How open hardware and software fit into Tenstorrent’s broader compute roadmap.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Learn more about this Employer on their Career Site

Staff Engineer, CPU Architectural Verification