Back to search
Description
The role involves pathfinding studies in silicon development phase where feedback is provided to silicon and packaging team on system integration tradeoffs. Ability to complete target impedance analysis, transient voltage droop and phase margin/stability analysis is required. The candidate is expected to guide and work closely with the system team on the component selections, for optimum power solutions with high and low load transient, at different performance state. The candidate is expected to work closely with System Design teams to provide detailed layout strategy and guidelines during design execution phase. The candidate is also expected to work with HW Validation teams to develop test-suites to perform system-level validation for evaluation of design margins on the power domains. The roll includes the power integrity support throughout the product design process which can include system pathfinding and verification stages, and characterization reviews with continuing guidance through production and ramp.
Minimum Qualifications
M.S Degree with 4~7 years relevant work experience. You must have proven technical understanding of power supply architectures covering voltage regulator technologies, power distribution network (PDN) modeling, PCB design practices and trade-offs for PDN design and optimization. Skills with associated tools for 2.5D (PowerSI, SIWave, Sentinel-PI, nSys), 3D Full wave (HFSS, nWave), quasi-static tools (Q3D, nApex) is required. Relevant proven understanding of HSPICE, Spectre, AMS, and Simplis models for system-level transient droop analysis is also vital. Understanding of die-package-board power delivery network co-design constraints and tradeoffs. Ability to work with multiple cross-functional teams to make the right trade-offs on the system performance is a must.
Preferred Qualifications
PhD with minimum 3-4 years experience. You should have a good understanding of multi-phase of Buck/Boost converter and LDO design principles, operating modes, and system integration care-about. Deep Experience in CPM (Chip-Power-Model) usage for system transient analysis is an added benefit. Hands-on experiences on package or board layout with Cadence tools is a plus. The candidate with this skill is expected to perform proof of concept layout study with Cadence tools. Experience with Python, MATLAB or other programming languages is desired. Excellent documentation and communication skills, ability to work independently and interest to mentor as well as demonstrated ability to innovate are required.
Learn more about this Employer on their Career Site
