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Description
Design and Development: Design, implementation, and verification of complex ASICs. Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based and formal verification teams to ensure robust design validation. Integration and Testing: Collaborate with hardware and software teams to integrate digital designs into complex SoCs. Timing and Power Analysis: Conduct timing analysis and power optimization to achieve PPA goals. Documentation and Reporting: Create detailed micro-architecture and design documentation.
Minimum Qualifications
Minimum of BS + 3 years relevant industry experience
Preferred Qualifications
Educational Background: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. Experience: 3+ years of proven experience in ASIC design, including RTL design and verification. Hands-on experience with ASIC design tools and methodologies is essential. Technical Skills: Proficiency in SystemVerilog, RTL design, synthesis, and timing analysis. Problem-Solving: Strong analytical and problem-solving skills. Collaboration: Excellent communication and teamwork skills, work effectively in cross-functional teams. Attention to Detail: Meticulous attention to detail and a commitment to delivering high-quality designs. Experience with high-speed I/O design and protocols. Knowledge of PCIe is a plus. Familiarity with custom ASIC design and FPGA prototyping. Hands on experience in all aspects of front-end chip development process (e.g., CDC/RDC, LINT, LEC, etc.). Knowledge of low-power design techniques and power optimization strategies.
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