Do you have a passion for solving the hardest problems in silicon? Do you thrive at the intersection of circuit theory, device physics, and hands-on failure investigation? As part of our Silicon Debug group, you'll take complex, often elusive silicon failures and systematically uncover their root cause — from electrical characterization all the way down to physical analysis. You and your team will apply deep engineering fundamentals and cutting-edge failure analysis techniques to enable product ramp at scale. Your efforts will directly impact the quality and reliability of state-of-the-art ASICs that power experiences for millions of customers worldwide. Join us, and you'll play a central role in ensuring the silicon we build is everything it needs to be. We have an extraordinary opportunity for Silicon Debug Engineers to investigate and root-cause failures in advanced custom digital megacells (SRAM memories, on-chip sensors, custom data paths) used in high-performance, low-power SoCs. You will bridge the gap between electrical debug and physical failure analysis, working at the frontier of silicon investigation.

Description

Imagine yourself at the center of our SoC bring-up and product ramp effort, collaborating across circuit design, process engineering, DFT, and failure analysis teams — with a critical impact on getting functional products to millions of customers quickly.

Minimum Qualifications

BSEE/MSEE

Preferred Qualifications

Experience in one or more of the following areas: SRAM circuits, custom circuit design, silicon debug. Experience in design or debug of low-voltage / low-power custom circuits. Deep understanding of deep-submicron device physics, leakage mechanisms, and technology interactions with device behavior. Solid understanding of device matching, device noise sources (1/f, thermal), extrinsic noise sources (supply noise, jitter), and their impact on high-precision circuits. Familiarity with electrical failure analysis (eFA) techniques and physical failure analysis (pFA) workflows, and the ability to plan FA strategies based on electrical debug data. Understanding of Dynamic Lock-in Thermography (DLS) and Lock-in Thermography (LIT) for localization of resistive and leakage defects, including their sensitivity limits and how thermal signatures correlate to specific circuit fault modes. Knowledge of Nanoprobe techniques for electrical probing of deep-submicron nodes, and appreciation of how probe contact, voltage bias, and electron beam exposure can perturb sensitive analog or memory circuits. Awareness of how physical sample preparation steps (deprocessing, FIB cross-section, delayering) can alter or destroy evidence of electrical failures, and how to coordinate FA plans that preserve failure signatures. Ability to interpret FA results (photon emission maps, OBIRCH, thermal maps, TEM/SEM imagery) in the context of circuit topology and failure electrical signatures. Ability to conduct structured experiments during silicon debug, gather and analyze large datasets, and utilize scripting to support efficient handling of debug data. Proficiency in scripting languages (Python, Perl, or others) and CAD automation tools. Knowledge of industry-standard circuit design and simulation tools.

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