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Description
Own all aspects of development design for large SOC blocks including: Internal and external IP integration, design of system bus and control bus logic for connectivity of IP blocks to main SOC infrastructure, ownership of the Integration Spec for the design project, integration and optimization of any memories and hard macros required for the block, run synthesis, netlist generation, and timing closure for the block Work closely with Chip Architecture, Design verification, Physical Design, DFT, and power teams to achieve first tapeout success on designs Develop and maintain methodology/flows/checks for your design Work with multi-disciplinary groups to make sure designs are delivered on time and with highest quality by incorporating proper checks at every stage of the design process
Minimum Qualifications
Enrolled in BSEE/MSEE, MSCE, or PhD program
Preferred Qualifications
Knowledge of the ASIC design flow, FE and Design verification, synthesis, scripting and netlist generation Proven track record of high performance designs for low power applications, RTL design and timing closure on large complex designs SOC IP integration and RTL Design for performance, low area, and low power FE synthesis with DFT insertion ASIC design flow and netlist flow checks - CDC, Logical Equivalence UPF flow for power islands as well as voltage islands Familiarity with DFT and backend related methodology and tools is a plus
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