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Description
In this job you will be responsible for translating custom mixed-signal circuit schematics into efficient SystemVerilog behavioral models for high level simulations. You will closely interact with circuit design teams to understand the details of custom circuits, and with DV teams to craft hooks for effective verification. You will run simulations and formal equivalence tools to ensure that the model matches closely with the custom circuits. You will code targeted checks within these representative models to ensure that the circuits are used as intended. You will write scripts and simple tools for automating repetitive tasks or performing calculations.
Minimum Qualifications
Bachelor’s degree Required.
Preferred Qualifications
Excellent knowledge of digital logic gates, clocking and state elements Excellent knowledge of Verilog/SystemVerilog with ability to write behavioral code Ability to read custom circuit schematics and understand functionality Solid understanding of logic and behavioral simulations Basics of passive and active circuit elements, voltage and current sources, and analog blocks like amplifiers ADCs/DACs/Comparators Basics of SPICE circuit simulations Basics of timing synchronous digital logic Familiarity of writing scripts in PERL/Python and basic algorithms is a strong plus Familiarity with blocks such as PLLs/DLLs/SERDES is a strong plus Basics of digital signal processing and numerical analysis is a plus Basics of probability and statistical basics is a plus
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