Staff Layout Design Engineer

AI Vision Processors For Edge Applications

Our solutions make cameras smarter by extracting valuable data from high-resolution video streams.

Job Description

As a member of the mixed signal IP team, the candidate work closely with IP designers on physical layout for mixed-signal IPs like PLL's, high speed I/O IPs, general I/O's, standard cells, and ESD structures designs in ub-micron CMOS technologies using Cadence/Mentor tools. Candidate will also work with cross team engineers to customize designs for integration in VLSI products. Floor planning, custom layout and verifying against schematics, design rules, and EM/Aging effect etc.

What we want to see:
• BSEE + 
• 3+ years of relevant mask design / layout experience
• Tape-out experience with FinFET technology is required. 
• Experience with high-speed SerDes design is helpful and Experience with top level integration would be excellent to have.
• Deep understanding of analog circuit layout concepts in submicron CMOS technologies
• Validated experience with Cadence custom circuit design tools - particularly virtuoso
• Experience running and debugging DRC/LVS/EMIR with verification tools such as Calibre
• Ability to work optimally in a team, good interpersonal skills and positive energy.
• Proficiency in scripting languages like perl, python, skill etc. is a plus
• Knowledge of DRC and LVS checking flows, ability to customize DRC and LVS decks