Analog Layout Engineer

Apple

Posted 2 days ago, valid for 12 days

Irvine, CA 92614, US

$90,000 - $108,000 per year

Full Time

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Sonic Summary

The Analog Layout Engineer position at Apple requires a self-motivated individual with a bachelor's degree and a strong understanding of analog layout fundamentals.
Candidates should have experience in driving consensus within a team and proficiency in interpreting and debugging Calibre results.
The role involves constructing layouts for various designs and working closely with circuit designers to ensure high-quality outcomes.
Preferred qualifications include knowledge of Unix and CAD environments, as well as experience with both planar and FinFET nodes.
The salary for this position is competitive, and candidates should ideally have several years of relevant experience in the field.

The team is searching for a self-motivating engineer for the role of Analog Layout Engineer. As a member of the Analog Layout team, you will be working on the leading-edge technologies to build best-in-class custom analog designs. You will become part of a development team that cultivates engineering excellence, creativity and innovation. Partnering across teams is a key component of success at Apple. Dynamic, smart people and inspiring, innovative technologies are the norm here!

Description

As a member of the Analog Layout team, you will construct layout for a wide variety of designs, in a wide variety of technologies. You will need to work closely with circuit designers as well as other layout designers to ensure you deliver the highest quality layout achievable.

Minimum Qualifications

Minimum requirement of a bachelors degree. Excellent verbal and written communication.

Preferred Qualifications

Good understanding of analog layout fundamentals, electromigration, IR drop, parasitics, LDEs, and ESD. Knowledge and understanding of Unix and CAD environments. Proficiency in interpreting and debugging Calibre results. Experience in driving/achieving consensus within the team. Experience covering both planar and FinFET nodes. SKILL scripting capability to improve efficiency.

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