At Apple, we work to craft products that enrich people’s lives. If you’re passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated DDR Design Engineer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple’s customers every single day. You will join the DDR PHY design team. We provide best-in-class PHY designs for high-performance, low power applications. As a logic design engineer, you will be involved in all phases of the design, from concept study, architecture definition, design and verification, to silicon bring-up and characterization.

Description

In this role, you will be responsible for performing concept studies and providing direction in terms of performance, gate count and power for various digital designs. You will be responsible for writing detailed design specification and test plans in close collaboration with architecture, circuit designers and verification engineers. You will provide high-quality RTL description, including assertions, for the design. Use formal tools and static checkers to guarantee RTL quality. You will also support design verification to insure bug-free first silicon. Responsibilities will include driving functional and code coverage as well as timing closure for your designs and supporting silicon bring-up, performance and power characterization.

Minimum Qualifications

BS degree in technical discipline with minimum 10 years of relevant experience

Preferred Qualifications

RTL design using Verilog or SystemVerilog, assertion writing. Design of state machines, data paths, arbitration and clock domain crossing logic. Logic synthesis, timing constraints. Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL. Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking. Prior experience in DDR PHY design and mixed-signal environment is a plus.

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