At Apple, we work every day to craft products that enrich people’s lives. If you’re passionate about tackling unsolved challenges, we have an exciting opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you early in your journey towards a chip design career and wish to challenge yourself in a technical and multi-disciplinary endeavor? If so, this is an exciting position in the world class Apple mixed-signal silicon design team! This position will build on a solid foundation in digital logic circuits and provide an introduction into understanding analog circuits. You will work with a variety of flows fundamental to modern silicon engineering: model and integrate high mixed signal and analog IPs into high-speed digital circuits ensuring formal equivalence between custom designs and their abstract representation. This is a great chance to gain valuable experience and knowledge in software methods and analysis, which are increasingly crucial across various disciplines. As a member of our wide-ranging group, you will have the exceptional opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every day. You will be working to specify, design, and help in the verification and lab bring-up of sophisticated mixed-signal circuits (digital side).

Description

In this job you will be responsible for specifying and/or micro-architecting digital blocks in sophisticated mixed-signal circuits. You will be responsible for RTL coding of blocks specified by you or others. You will also participate in the design verification and bring-up of such blocks by writing meaningful assertions, debugging code, and otherwise interacting with the design verification team. You will contribute to the lab bring-up of those circuits by potentially writing test scripts, analyzing lab data, proposing experiments, etc.

Minimum Qualifications

BS degree in technical discipline with minimum 10 years of proven experience.

Preferred Qualifications

Proven knowledge of RTL design, Verilog and SystemVerilog Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers) Strong communication and presentation skills Solid understanding of mixed signal concepts is a plus Validated knowledge of synthesis, static timing and DFT is a plus Validated knowledge of SystemVerilog assertions, checkers, and other design verification techniques are a plus Knowledge of scripting languages; Perl and Python are a plus

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