We are seeking an ASIC Power Engineer to drive SoC power simulation, analysis and optimization for next-generation wireless SOC products. This role requires deep technical expertise in power estimation and a passion for developing highly power-efficient SoCs that enable breakthrough wireless experience.

Description

In this highly visible role, you will be responsible for SoC power estimation, use case power analysis, and driving future SoC power optimization strategies. You will work with a team of talented engineers to integrate innovative power solutions and deliver industry-leading power efficiency. The position focuses on SoC power estimation and optimization for power-critical wireless products. - Work with architects to define power-critical use cases and scenarios. - Establish power targets and collaborate with cross-functional teams to achieve optimization goals. - Define comprehensive test cases within design verification environments. - Generate accurate pre-silicon power estimations for design decision-making. - Analyze power consumption patterns and identify optimization opportunities. - Develop SoC power models for new architecture designs, enabling performance/power trade-off analysis. - Understand software and system-level interactions that impact overall power consumption. - Partner with lab and silicon characterization teams to correlate models with measured silicon data.

Minimum Qualifications

BS in Electrical Engineering, Computer Engineering, or related technical field Hands-on experience with PtPx and PPRTL power analysis tools. Proficiency in scripting languages including Python, Perl, or TCL.

Preferred Qualifications

Understanding of electrical properties of on-die PDN, power gating, package and system power delivery. Hands-on experience with SoC power domains and power management unit (PMU) interactions in complex multi-core chipsets. Knowledge of power impact at architecture, logic design, and circuit levels. Experience in power model development for complex SoCs. Familiarity with SoC design flow and methodology. Strong communication skills to collaborate effectively across multiple engineering disciplines. Knowledge of WiFi or Bluetooth standards and protocols. Experience in SoC power simulation, modeling, and analysis flow development. Experience in ASIC power estimation, analysis and optimization methodologies. Experience in power model development for IPs. Hands-on experience in correlating pre-silicon power models with measured silicon data and driving model accuracy improvements through systematic debugging.

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