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Description
In this role you will work on a small team designing CPU-based subsystems for high performance, low power wireless SoCs. You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals. You will own the design for the debug and trace hub. You will collaborate with other designers to ensure their subsystems implement the necessary debug features. You will guide validation engineers in the use of such features to diagnose issues. This is a highly visible role, where you will be at the center of the ASIC debug efforts, collaborating with all fields, with a critical impact in getting leading-edge products launched to delight millions of customers.
Minimum Qualifications
Minimum requirement of bachelor's degree
Preferred Qualifications
Familiarity with the ASIC design flow. Knowledge of digital design, SoC architecture, and HDL languages like Verilog. Familiarity with design methodologies and industry standard EDA tools. Knowledge and understanding of microprocessor debug such as CoreSight and other debug techniques. Shown experience writing micro-architecture specifications and converting them to design. Experience with AXI/AHB bus fabric and processor sub-systems. Understanding of UPF and low-power design & implementation techniques. Self-starter and willingness to learn.
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