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Product Engineer (Yield & Quality)

TSMC
Posted 3 months ago, valid for 8 days
Location

Phoenix, AZ 85001, US

Salary

Competitive

Contract type

Full Time

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Sonic Summary

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  • TSMC Arizona is seeking Product Design Engineers for its 5-nanometer fab in Phoenix, Arizona, offering a dynamic environment for innovation.
  • The role requires a Master's Degree in Electrical Engineering and a minimum of 6 to 9 months of training in Taiwan.
  • Candidates should possess knowledge of semiconductor physics and digital circuit design, along with strong problem-solving and communication skills.
  • Responsibilities include analyzing chip performance issues, leading teams to identify root causes, and supporting early-stage product design.
  • While the salary is not specified in the job description, successful applicants will be part of a company that values integrity, commitment, and innovation.

Product Design Engineer, Yield & Quality

 

At TSMC Arizona, brilliance can ignite a world of innovation and launch a promising future. The world’s most brilliant innovators entrust us to transform their ideas into world-changing products that impact millions of lives. As long as you have the same passion to pursue excellence, you will find your fit here.

 

TSMC Arizona is looking for Product Design Engineers to join our 5-nanometer fab, located in sunny Phoenix, Arizona. As a Product Engineer, you will demonstrate a strong sense of reliability and enthusiasm and will possess an attitude that embodies our core values – Integrity, Commitment, Innovation and Customer Trust.

 

TSMC Arizona’s Product Designer is responsible for early-stage design, yield window performance, and identify root cause for chip performance.

 

Job Description:

  • Lead team to identify root cause for N5/N4 chip performance / yield / quality issues:
  • Analyze CP test bin / data log to identify failure mode
  • Electrical failure analysis and physical failure analysis to locate suspect process stage
  • Work with Fab integration team or process team to define corrective actions / solutions
  • Trace action implementation to verify effectiveness
  • Product early-stage design support to help product tape-out smoothly and Si success:
  • Design rule review & assessment for robust product design
  • Layout review or DFM to enlarge manufacturing window
  • Yield window characterization and device sweet spot identification for the best yield / performance process condition.

 

Minimum Qualifications:

  • Applicants must be legally eligible to work in the United States and have:
  • The ability to travel and train in Taiwan for 6 – 9 months
  • Master’s Degree in Electrical Engineering, required
  • Working knowledge of semiconductor physics, CMOS device operation, and advanced semiconductor manufacturing is preferred
  • Familiar with digital circuit design is preferred.
  • Able to work within cross-functional teams.
  • Consistent problem-solving skills, communication abilities, and active learning
  • Able to work under pressure and mission orientation

 

 

Work Location: Phoenix, AZ

Training Location:  Phoenix

Travel Percentage:  As Required




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