Silicon Engineer- P and D- (gCPU), Architect & Performance (multiple openings)

Minimum qualifications:

• Bachelor’s degree in Electronics or Electrical Engineering, Computer Science, Computer Engineering, or a related field and 4 years of experience in the job offered or in a Silicon Engineer-related occupation.
• Alternatively, will accept a Master’s degree in Electronics or Electrical Engineering, Computer Science, Computer Engineering, or a related field and 2 years of experience in the job offered or in a Silicon Engineer-related occupation.
• Position requires: 2 years of experience in High-performance microprocessor microarchitecture development, performance modeling, or performance correlation; 1 year of experience in C or C++, and scripting languages; and Education in computer architecture, including high-performance CPU architecture.

About the job:

The US base salary range for this full-time position is $169,000 - $198,000 + 15% bonus target + equity + benefits determined by role, level, and location. Individual pay is determined by additional factors, including job-related skills, experience, and relevant education or training. Learn more about benefits at Google.

Position reports to the Google Portland, OR office & may allow for a hybrid schedule as per Google policy.

The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Responsibilities:

• Build/enhance modeling infrastructure and develop performance models for performance analysis and microarchitecture exploration. 
• Conduct workload analysis for microarchitecture exploration. 
• Study and define high performance, low power CPU microarchitecture. 
• Conduct performance correlation between the performance model and RTL implementation, including micro-benchmark development and performance bug triage.