Director DFT & Test

About GlobalFoundries

GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com.

Summary of Role:

The DFT and Post-Silicon Test Manager leads and develops the engineering team responsible for designing, verifying, and validating advanced Design-for-Test and post-silicon test solutions in semiconductor chip development. This role focuses on building robust DFT architectures—including ATPG, MBIST, LBIST, analog and boundary scan test—and extending them into efficient post-silicon validation, bring-up, and production test strategies. The position emphasizes seamless integration between pre-silicon design validation and post-silicon characterization to achieve rapid, high-quality silicon ramp-up.

Essential Responsibilities:

• Lead, mentor, and manage the DFT and post-silicon test engineering team, overseeing technical direction, execution, and development.

• Define and deploy end-to-end test architecture from design insertion through silicon validation, covering ATPG, MBIST, LBIST, boundary scan (JTAG/IEEE 1149.x), analog test structures, and built-in monitors.

• Develop and optimize scan compression and test pattern generation flows, balancing coverage, test time, and yield learning.

• Own post-silicon test planning, including validation vectors, ATE correlation, and silicon bring-up strategies.

• Interface closely with design, verification, product engineering, and ATE teams to ensure smooth handoff from simulation to tester.

• Develop automated test programs and diagnostic scripts supporting wafer sort, package test, and system-level characterization.

• Analyze silicon test data for root-cause isolation, yield improvement, and continuous DFT methodology refinement.

• Build infrastructure for post-silicon debug and failure analysis, including test coverage tracking and bin management.

• Evaluate and deploy next-generation DFT and post-silicon validation tools, methodologies, and standards.

• Document test specifications, qualification methodologies, and re-use frameworks for ongoing improvement.

Other Responsibilities: 

• Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs

Required Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

• 15+ years of hands-on experience across DFT and post-silicon validation, with proven leadership of SoC-level test teams.

• Expertise in ATPG, MBIST, LBIST, scan compression, boundary scan, analog/mixed-signal test, and fault modeling.

• Practical experience with post-silicon silicon debug, ATE vector bring-up (e.g., Teradyne, Advantest), and yield analysis.

• Ability to correlate pre-silicon and production test environments, including diagnostic log analysis and tester pattern debug.

• Proficiency with major EDA tools (Synopsys, Cadence, Siemens/Mentor) and scripting (Python, Perl, TCL).

• Strong understanding of test coverage metrics, fault simulation, and data-driven test improvements.

• Excellent leadership, planning, and communication skills across cross-functional teams.

Preferred Qualifications:

• Strategic thinker who understands full-lifecycle test—from design insertion to production ramp.

• Innovative leader who drives collaboration between DFT, characterization, and product engineering.

• Passionate about test time reduction, yield learning, and robust field quality metrics.

• Continuous learner who proactively evaluates tools, methods, and automation opportunities.

Expected Salary Range

The exact Salary will be determined based on qualifications, experience and location.