Description
As a member of Emulation verification team, you will play a key role in utilizing Emulation for verification of large Wireless SoCs. You will also be involved in the most cutting-edge technology of bringing in mixed signal models onto the Palladium platform. The overall work will involve porting the design onto the Palladium platform, followed by executing the detailed Emulation testplan.
Minimum Qualifications
Minimum requirement of a bachelor’s degree Experience with System Verilog, Verilog or UVM
Preferred Qualifications
Experience with bring up, debugging and verification in Emulation Understanding of the tool flow from RTL to Emulation Good understanding of any Standard Emulator (Palladium, Veloce, Zebu) OR FPGA (Xilinx, Altera) flow Proven Design Verification or Silicon Validation skills Experience in writing Synthesize-able SystemVerilog/Verilog code and SystemVerilog assertions Experience with System Verilog verification environments including C/C++ DPI, UVM Experience on any Scripting (Perl/Python/TCL) Excellent analytical and debug skills Hands on usage of Low Power methodologies (UPF based preferably) Experience in UVM Acceleration
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