Lead SoC Performance & Power Engineer

About the role

As our Lead Performance architect, you'll drive the architectural configuration, system-level simulation, and PPA optimization of the chiplet by using industry-standard ESL tools and / or developing  in-house tools to integrate and calibrate highspeed I/O IPs such as PCIe, UCIe and Ethernet as well as NoC fabric into a system. You'll own the trade-off analysis that define what we tape out.

Responsibilities

• Own PPA exploration and trade-offs between peak performance, silicon area, and thermal/power budgets, and turn that into clear tape-out recommendations.

• Build transaction-level models (TLM) using commercial ESL suites (e.g. Platform Architect) that integrate third-party IPs such as PCIe, UCIe, and NoC etc into a full-chiplet model.

• Define, sweep, and validate hardware configuration parameters — buffer sizes, queue depths, clock-domain crossings, routing tables — to maximize throughput and minimize latency across realistic workloads.

• Characterize traffic across the internal NoC and the UCIe die-to-die interface to find congestion points and rule out protocol deadlocks before they reach silicon.

• Work directly with our IP vendors to debug model/behavioral mismatches, report performance anomalies, and integrate new IP deliverables as they land.

Required

• BS/MS in Electrical Engineering or related field with 6+ years in computer architecture, performance modeling, or microarchitecture configuration.

• Direct, hands-on experience with commercial ESL tools such as Platform Architect, Virtualizer, or comparable frameworks.

• Solid working knowledge of at least one of: PCIe (Gen 5/6/7), UCIe, or AMBA NoC protocols (AXI/CHI) — and a willingness to get deep on the others.

• Strong Python for automating large-scale simulation sweeps, parsing performance reports, and analyzing results.

• Familiarity with SystemC and transaction-level modeling paradigms — enough to write custom traffic generators when the off-the-shelf models fall short.

Nice to have

• Fluency with power modeling or floor-planning trade-offs.

• Prior work on a multi-die / chiplet program, or hands-on UCIe die-to-die.

• Experience taking architectural models through to a real tape-out.