About the Company:

At SK Hynix Memory Solution, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape.

We're looking for innovative minds to join our mission of shaping the future of technology. At SK Hynix Memory, you'll be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change – we're driving it, with significant investments in artificial intelligence, machine learning, and eco-friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing.

About the Role: Join our Physical Design team to help deliver next-generation SSD controller chips. As a Physical Design Intern, you will collaborate with experienced engineers to transform RTL designs into functional physical layouts. You will gain hands-on experience in the complete ASIC flow from synthesis to tape-out, working on real projects in a fast-paced, innovative environment.

Responsibilities:

Execute ASIC physical design implementation flows, including floorplanning, placement, clock tree synthesis (CTS), and routing.
Perform static timing analysis (STA) and work to resolve setup and hold timing violations.
Run and analyze design rule checks (DRC) and layout versus schematic (LVS) checks to ensure design integrity, as well as IR-Drop analysis.
Assist in optimizing power, performance, and area (PPA) metrics using industry-standard EDA tools.
Developing entire P&R/physical verification/IR-EM flows.
Collaborate with front-end design and verification teams to seamlessly integrate RTL changes and resolve physical design constraints.
Help generate and maintain physical design scripts, utilities, and documentation for the team.

Minimum Qualifications:

Currently pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
Foundational understanding of VLSI design concepts, CMOS circuit design, and digital logic.
Familiarity with the basic stages of the ASIC physical design flow.
Academic or project experience with scripting languages such as Python, Perl, or TCL.
Strong analytical and problem-solving skills with a high attention to detail.

Preferred Qualifications:

Hands-on coursework or project experience with industry-standard EDA tools (e.g., Synopsys ICC2, Cadence Innovus, or similar).
Exposure to Static Timing Analysis (STA) concepts and tools (e.g., PrimeTime, Tempus).
Basic understanding of design constraints (SDC) and library exchange formats (LEF/DEF).
Knowledge of low-power design techniques and power intent formats (UPF/CPF).
Familiarity with AI/LLM tools (e.g., GPT, Copilot) and prompt engineering, with the ability to leverage them to automate EDA scripting, analyze design data, or optimize workflows.

COMPENSATION: $35/hr - $45/hr

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