SoC/IP Power Analysis and Optimization Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  

THE ROLE:

AMD-Xilinx is seeking a capable and motivated SoC Design Engineer to be part of Front-End SoC Design Team. In this role, you will focus on power analysis and optimization to help design high performance and power efficient SoCs.

THE PERSON:

• The ideal candidate should have a solid background in SoC design with strong knowledge of power reduction techniques.
• You should be proficient in interpreting results from power estimation tools and translating them into effective power optimization strategies.
• The candidate should demonstrate strong analytical thinking and problem-solving abilities.
• Excellent communication skills, along with the ability to work effectively in a collaborative, team-oriented environment.

KEY RESPONSIBILITIES:

• Understand power requirements, establish the baseline, create a strategy to meet requirements, monitor the evolution of the design, and guide the team towards meeting power requirements.
• Report status periodically to stake holders.
• Perform vector-based and vector-less power estimation for different use case scenarios and analyze results to identify areas for improvement.
• Drive static and dynamic power analysis and optimization for complex SoCs and IP blocks.
• Drive low-power design strategies.
• Power domain/island creation (with UPF).
• Develop and maintain power analysis flows using industry-standard EDA tools and emerging, cutting-edge methodologies.
• Correlate RTL power estimates with gate-level and post-layout power results.
• Contribute to definition/evolution of SoC Design methodologies and processes for future projects. 

PREFERRED EXPERIENCE:

• A successful candidate will have an SoC/ASIC design background, would have participated in several silicon design projects with increasing level of scope/responsibilities in managing power optimization through the project life cycle.
• Expertise with low-power design methodologies and trade-offs.
• Hands-on expertise with EDA tools such as PrimeTime, PrimePower, Power Artist.
• Experience with RTL design and analysis (Verilog/System Verilog).
• Experience designing with multiple power domains and islands using UPF.
• TCL, Python, Perl scripting, familiarity with AI tools such as Claude, Codex.

ACADEMIC CREDENTIALS:

• Bachelor’s or master’s degree in electrical or computer engineering.

LOCATION: San Jose, CA

This role is not eligible for visa sponsorship.

#LI-RW1

#LI-HYBRID

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.