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Product Development Engineer

Advanced Micro Devices, Inc
Posted 4 months ago, valid for 9 days
Location

San Jose, CA 95103, US

Salary

USD 0 - 0 YEAR

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Contract type

Full Time

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Sonic Summary

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  • AMD is seeking a candidate to develop characterization and silicon validation plans for high-speed transceivers.
  • The role requires experience in characterizing PLL, CDR, and TX/RX analog front-end, along with hands-on laboratory experience using various lab equipment.
  • Candidates should possess a BSEE/MSEE degree and extensive experience in product characterization or validation, with skills in Verilog, Python, Perl, and TCL.
  • The position is located in San Jose, CA, and is not eligible for visa sponsorship.
  • Salary details are not provided in the job description, but the role typically requires several years of relevant experience.


WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  




KEY RESPONSIBILITIES:

  • Develops characterization and silicon validation plans for high speed transceivers
  • Defines methodologies for characterization and silicon validation of high speed serial systems
  • Characterize high speed SERDES with automated flows
  • Data analysis and create characterization reports
  • Correlation of pre-silicon results with silicon measurements
  • Drives direct and cross-functional teams to expand capability, productivity and effectiveness to deliver improvements in cost, quality and manufacturability

 

PREFERRED EXPERIENCE:

  • Experience in characterizing PLL, CDR, TX/RX analog front-end
    • PLL phase noise measurement, transmitter output jitter measurement, receiver jitter tolerance measurement
  • Hands on experience in laboratory environment, using lab equipment such as sampling oscilloscope, high performance BERT, logic analyzers, spectrum analyzers, BERT scopes, function/pulse generator
  • Experience in transceiver electrical compliance testing (PCIE, IEEE 802.3, OIF-CEI)
  • Experience in using automated methodologies to maximize use of equipment
  • Experience working with FPGA and/or SOC Architectures
  • Understanding of PCB schematic and layout
  • Strong analytical, problem-solving and debugging skills
  • Experience in protocol testing (PCIE, SATA, SGMII, 100GBASE-X)
  • Skills: Verilog, Python, Perl, TCL

 

ACADEMIC CREDENTIALS:

BSEE/MSEE with extensive experience in product characterization or validation field

 

LOCATION:

San Jose, CA

 

This role is not eligible for visa sponsorship.

 

#LI-TW2

#LI-HYBRID




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.




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