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95052, Santa Clara, CA
ASIC Design Engineer - Cache Controller

ASIC Design Engineer - Cache Controller

Apple

Posted 5 months ago, valid for 24 days

Santa Clara, CA 95052, US

Competitive

Full Time

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Sonic Summary

Apple is seeking a candidate with 3+ years of full-time ASIC design experience for a role focused on developing hardware for cache subsystems in high-performance system on a chip (SoC).
The position involves designing and developing cache micro-architecture based on architectural guidelines and conducting performance, power, and area (PPA) analysis.
Candidates should have a solid understanding of cache design, memory organizations, and multi-processor cache coherence protocols.
The role also requires collaboration with the physical design team for timing closure and debugging register-transfer level (RTL) designs.
While a B.S. in a relevant field is required, a Master's degree is preferred, and the salary for this position is competitive within the industry.

Apple is building the world’s fastest highly parallel mobile processing systems. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. As we increase levels of parallelism, bandwidth and capacity, we are presented with design challenges exacerbated by clients with varying but simultaneous needs such as real-time, low latency, and high-bandwidth. In this role, you will work on crafting special purpose cache and controller which is part and parcel of the SOC memory hierarchy.

Description

Design and develop hardware for cache subsystem in high performance system on a chip (SoC). Develop cache micro-architecture based on architecture guidelines and model analysis. Explore architecture trade-offs in system performance, area, and power consumption. Develop and debug register-transfer level (RTL) design of various sections in the cache subsystem. Work on front-end netlist and area/timing analysis of the cache subsystem. Work with physical design team on the timing closure of the cache subsystem.

Minimum Qualifications

3+ years of full time ASIC design experience memory system development RTL/micro-architecture definition PPA (performance/power/area) analysis B.S. in a relevant field

Preferred Qualifications

Cache design background including good understanding of different memory organizations and tradeoffs Experience with multi-processor cache coherence protocols Knowledge of high-performance coherent memory systems or interconnect architectures Knowledge of high-performance DRAM controller M.S in a relevant field.

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ASIC Design Engineer - Cache Controller

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Minimum Qualifications

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