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Description
Imagine yourself at the center of our hardware development effort. In this role, on memory compiler, you will collaborate with compiler vendors and design teams. You will have the opportunity to integrate and come-up with new ideas, as well as work with a team of dedicated engineers. You will work closely with compiler development and deployment to impact PPA of the end products. In this exciting role, you will perform the following: - Drive the development of SRAM, register files and latch arrays to enable high performance and low power design - Have as comprehensive understanding of IC compilers that are available globally - Lead the SRAM compiler IP requirements to Vendors and the internal IP teams - Understand the complete spectrum of design flow, DFT and testing aspects of the compiler IPs - Work with logic/architecture team to capture specifications of SRAM/Reg files/Latch arrays and drive the implementation.
Minimum Qualifications
BS and a minimum of 10 years of relevant industry experience
Preferred Qualifications
We are looking for applicants with at least 5+ years circuit design experience Expertise in developing high-performance low power circuit design and SRAM and register file arrays Deep knowledge of industry standard circuit simulation and design tools, top-level integration tools Experience in leading multi-functional teams by technical expertise and to present sophisticated technical topics to a multi-level audience Proven understanding of device physics and process Drive multi-functional team for failure analysis, corrective action implementation plan and yield bridge to a successful ramp & mass production Exposure to ML based programming algorithms Ability to provide automations for rapid and dynamic design needs
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