Description
In this role as a CPU Implementation Silicon Correlation Engineer, you will be working on the following: • Obtain process-related silicon measurement data from product and technology team • Analyze pre-silicon timing runs to comprehend margins and relate it to measured silicon parameters • Work with post-silicon teams in evaluating ROI of design and methodology features •Analyze post-silicon speed debug data to help identify and root cause failing paths
Minimum Qualifications
Minimum BS and 10+ years of relevant industry experience Experience with a chip tapeout of a custom or PnR block Experience with STA Experience running spice simulations and analysis Experience with data parsing, analysis, and representation/plotting skills
Preferred Qualifications
Chip design experience including experience in CPU design Good understanding of std cell architecture and design Working knowledge of device technology and spice models Familiarity with ATPG pattern framework Awareness of PNR tool flows Language proficiency in TCL, Perl, and Python Ability to work with cross-functional teams spanning pre-silicon design, technology and post-silicon debug
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