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CPU Physical Design and Integration Engineer

Apple
Posted 2 days ago, valid for a month
Location

Santa Clara, CA 95052, US

Salary

Competitive

Contract type

Full Time

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Sonic Summary

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  • Apple is seeking a CPU Physical Design and Integration Engineer with a minimum of a BS degree and experience in place and route and physical verification.
  • The role involves responsibilities such as chip level place and route, final CPU layout database construction, and collaboration with various teams to ensure timely product delivery.
  • Candidates should possess proficiency in a scripting language like Perl or Tcl, and familiarity with industry-standard design tools is preferred.
  • The position requires strong problem-solving skills, teamwork, and knowledge of CMOS circuit design and physical construction fundamentals.
  • The salary for this position is competitive, and applicants should ideally have several years of relevant experience in processor development.
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish! Dynamic, thoughtful people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want join us in these pursuits? Join us to help deliver the next groundbreaking Apple product! In this highly visible role, you will be at the center of a processor design effort collaborating across domains, with a critical impact on getting functional products to millions of customers quickly.

Description


As a CPU Physical Design and Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Block partitioning and pin placements • Own chip level place and route (PnR), final CPU layout database construction, and verification (PDV) • Work with the Implementation/CAD teams during the entire chip design cycle to drive signoff closure for tapeout • Work with the SOC team to meet IP technical and delivery requirements • Participate in flow development for chip integration and analysis • Scripting to automate tasks and improve debug efficiency including genAI initiatives

Minimum Qualifications


Minimum BS degree. Experience with place and route and physical verification. Experience with a scripting language such as Perl or Tcl.

Preferred Qualifications


Knowledge of industry standard place and route tools and practices in physical design. Fundamentals of physical construction, PDV, DRC/LVS verification. Working knowledge of Python. Understanding of CMOS circuit design. Layout design background. Working knowledge of extraction, STA, EMIR concepts. Ability to work well in a team, being an excellent problem solver, and self-motivated.



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