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CPU Physical Electrical Analysis Engineer

Apple
Posted 3 months ago, valid for 13 days
Location

Santa Clara, CA 95052, US

Salary

Competitive

Contract type

Full Time

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Sonic Summary

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  • Apple is seeking a CPU Physical Electrical Analysis Engineer to drive the design and analysis of high-performance compute blocks.
  • Candidates should have a minimum of a Bachelor's degree and at least 3 years of relevant industry experience.
  • The role involves working on power grid design and collaborating with various teams to ensure design quality and schedule adherence.
  • Preferred qualifications include knowledge of computer architecture, experience with TCL-based automation, and familiarity with industry-standard tools.
  • The position offers a competitive salary, although the specific amount is not disclosed in the job description.
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish! Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product! As a CPU Physical Electrical Analysis Engineer, you will be driving the block and top level design of power-grid and analysis of high performance compute blocks in the EMIR/SIGEM/Reliability space.

Description


• Drive block and top-level EMIR/electrical verification closure • Work on power grid design, construction, and implementation using existing infrastructures and where necessary, creating custom solutions in PNR tool environment • Work multi-functionally with CAD/EDA vendors to ensure fidelity of analysis results; with methodology teams to cover unique use cases; with implementation teams to drive design and sign-off closure, and with the SoC level teams to meet IP delivery quality and schedule

Minimum Qualifications


Minimum BS and 3+ years of relevant industry experience Experience with PNR design implementation and STA

Preferred Qualifications


Knowledge of computer architecture and RISC pipelines Experience in TCL-based automation with PNR & STA tools Familiarity with industry standard tools such as Siemens, Ansys Redhawk, Seascape, or Cadence Voltus Working knowledge of C/C++ Ability to write and maintain scripts in TCL, Python, or Perl Experience with data analysis techniques using Python or Perl Experience with matplotlib / pandas or similar data analytics packages



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