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  3. Graphics Power Analysis & Optimization Engineer

Graphics Power Analysis & Optimization Engineer

Apple
Posted 22 days ago, valid for a month
Location

Santa Clara, CA 95052, US

Salary

Competitive

Contract type

Full Time

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Sonic Summary

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  • The role involves creating solutions for complex challenges in the design and manufacturing of high-performance, power-efficient processors and systems-on-chip (SoC) for Apple products.
  • Candidates must have strong analytical skills and a background in power, micro-architecture, and scripting, particularly in Python.
  • A minimum of 10 years of relevant experience is required, along with expertise in low power microarchitecture and tools like PowerArtist and PTPX.
  • The job includes activities such as power estimation, analysis, and optimization for GPU designs, as well as developing flows to enhance power analysis coverage.
  • Excellent communication skills and self-motivation are essential for success in this role.
Do you love creating elegant solutions to highly complex challenges? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC)! You’ll ensure Apple products and services can seamlessly handle the tasks that make them beloved by millions. Joining this group means you’ll be crafting and building the technology that fuels Apple’s devices. Together, we enable our customers to do all the things they love with their devices! We are looking for a talented and creative engineer to support the power activity of Apple best-in-class GPU development.

Description


For this role, the candidate must have strong analytical skills and background in power, micro-architecture and scripting to support the following activities on GPU designs: - Create early power estimation, power targets and perform what-if analysis at architectural evaluation stage. - Support RTL and gate-level power rollup and analysis. - Analyze various GPU workloads to identify power reduction opportunities. - Evaluate and implement power optimizations in both RTL and gates. - Identify the best power sign-off tests to improve power analysis coverage. - Develop flows & heuristics to accelerate power triage on large power data sets.

Minimum Qualifications


Experience with low power microarchitecture and implementation. Experience with scripting in Python. Experience with PowerArtist and/or PTPX. BS degree and minimum of 10+ years of relevant experience.

Preferred Qualifications


Experience in product level power budgeting and projection. Experience in writing, simulating and debugging RTL designs. Experience in low power ASIC design and implementation techniques. Experience in data mining applications to power modeling & triage. Experience in power use-case definition and analysis. Experience in post-silicon power correlation. Experience in power management techniques. Excellent communication skills, self-motivated and well organized.


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