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Graphics Power Analysis & Optimization Engineer

Apple
Posted 23 days ago, valid for 25 days
Location

Santa Clara, CA 95052, US

Salary

Competitive

Contract type

Full Time

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Sonic Summary

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  • The position is for an engineer in Apple's Silicon Technologies group, focusing on power activity for GPU development.
  • Candidates should have a minimum of a BS degree and experience with Verilog, SystemVerilog, and Python scripting.
  • The role involves creating power estimations, analyzing GPU workloads, and implementing power optimizations.
  • Preferred qualifications include knowledge of digital logic design, VLSI power fundamentals, and low power design techniques.
  • The salary for this position is competitive, though not specified, and candidates should possess strong analytical skills and relevant experience.
Do you love creating elegant solutions to highly complex challenges? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC)! You’ll ensure Apple products and services can seamlessly handle the tasks that make them beloved by millions. Joining this group means you’ll be crafting and building the technology that fuels Apple’s devices. Together, we enable our customers to do all the things they love with their devices! We are looking for a talented and creative engineer to support the power activity of Apple best-in-class GPU development.

Description


For this role, the candidate must have strong analytical skills and background in power, micro-architecture and scripting to support the following activities on GPU designs: - Create early power estimation, power targets and perform what-if analysis at architectural evaluation stage. - Support RTL and gate-level power rollup and analysis. - Analyze various GPU workloads to identify power reduction opportunities. - Evaluate and implement power optimizations in both RTL and gates. - Identify the best power sign-off tests to improve power analysis coverage. - Develop flows & heuristics to accelerate power triage on large power data sets.

Minimum Qualifications


Experience with Verilog and SystemVerilog. Experience with scripting in Python. Minimum requirement of BS degree.

Preferred Qualifications


Knowledge of digital logic design principles including power and timing implications. Experience with VLSI power fundamentals: dynamic & leakage. Experience with low power design: clock gating, data-gating. Excellent communication skills, self-motivated and organized.



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