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Memory Packaging Engineer

Apple
Posted 9 days ago, valid for 22 days
Location

Santa Clara, CA 95052, US

Salary

Competitive

Contract type

Full Time

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Sonic Summary

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  • Join Apple's team as a Memory Packaging Engineer, where you will innovate memory solutions for their products.
  • This role requires a minimum of 10 years of relevant industry experience and a BS degree, with an MS or PhD preferred.
  • You will be responsible for the development and qualification of next-generation memory packages, impacting millions of users.
  • Candidates should have strong knowledge of thin-die stacking technologies and packaging materials to address thermal challenges.
  • The position offers a competitive salary, reflecting the expertise and experience required for this critical role.
Join the team at the heart of memory innovation for every Apple product. As a Memory Packaging Engineer, you will architect the memory solutions that power the industry-leading performance of Apple's hardware. We push the boundaries of bandwidth density, power efficiency, and system integration through meticulous co-design between memory technology and our world-class systems. If you are driven to solve the industry's toughest packaging challenges, your work will have a profound and lasting impact on the products used by millions.

Description


In this role, you will drive the definition, development, and qualification of next-generation memory packages critical to Apple’s future products. You will guide the package roadmaps of our memory partners and collaborate with internal engineering teams to enable bandwidth and density scaling. Your ownership will span the entire product lifecycle, from initial concept through qualification.

Minimum Qualifications


BS and 10+ years of relevant industry experience

Preferred Qualifications


MS or PhD preferred, with 10+ years of industry experience in package design and assembly process development of high-bandwidth and high-density memory packages. Strong knowledge of thin-die stacking technologies including wirebond, flip-chip, and wafer/die bonding. Strong knowledge of packaging materials and design to engineer warpage and CTE properties and mitigate thermal challenges. Solid working experience in package test and reliability, system-level downstream process interaction, and packaging inspection metrology. Deep understanding of SI/PI co-design with memory die and high-speed DDR or differential signaling. Understanding of how memory die floorplan and architecture influence package structure and routing, with experience collaborating with memory die design teams. Excellent communication skills for collaborating with internal teams and managing external vendors.



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