Senior Principal Switch Architect

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

What You Can Expect

As a Senior Principal Engineer, you will serve as a key technical leader driving architecture and execution for next-generation Teralynx switch products. You will:

• Define new features, pipelines, and protocols for next-generation data center switch chips.
• Deliver detailed behavioral and performance models to validate architectural decisions and ensure scalability for cloud-scale deployments.
• Drive end-to-end switch architecture from high-level concept through micro-architecture engagement and silicon bring-up.
• Partner with cross-functional engineering teams to ensure architectural intent is delivered through implementation and verification.
• Analyze tradeoffs across latency, throughput, memory architecture, power, area, and QoS to guide design decisions.
• Participate in customer-facing technical discussions, aligning product capabilities with real-world use cases and requirements.
• Contribute to long-term architectural direction and roadmap planning for the Teralynx product line.
• Mentor engineers, share best practices, and elevate architectural rigor across the organization.

What You Can Expect

• High ownership and visibility in defining and guiding major architectural features of Marvell’s flagship switch products.
• A deep, hands-on role in shaping silicon that scales to the next generation of cloud and AI data centers.
• A highly collaborative on-site engineering culture that accelerates problem solving and innovation.
• Opportunities to work across domains — hardware, software, systems, and customer engineering — broadening your technical influence.
• A stable environment with the resources of a global semiconductor leader, paired with the agility of a fast-moving product organization.
• A compensation and benefits package designed to attract top technical talent.

What We're Looking For

• Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, or related field and 15+ years of relevant experience, OR
• Master’s/PhD with 10–12+ years of experience in semiconductor architecture or ASIC development.
• Strong background designing or architecting complex ASICs, ideally in networking or switch domains.
• Deep knowledge of Layer 2 / Layer 3 forwarding, QoS, congestion management, and networking protocols.
• Expertise with behavioral and performance modeling, architectural validation, and system-level tradeoff analysis.
• Strong programming skills in C/C++ and Python.
• Demonstrated ability to collaborate effectively across geographies and multi-disciplinary engineering teams.
• Excellent communication skills with the ability to explain complex architectural concepts clearly and persuasively.

Preferred / Nice-to-Have

• Experience with multi-die / chiplet architectures, die-to-die interfaces, or advanced packaging.
• Familiarity with switch pipeline architectures, buffer management, traffic engineering, and programmable datapaths.
• Experience engaging with customers or standards bodies.
• Published papers, patents, or previous leadership roles in architecture teams

Expected Base Pay Range (USD)

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements 

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity
 

As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.
 
Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.