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Responsibilities
- Develop functional tests based on verification test plan.
- Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.
- Define and implement ASIC verification plans, build verifications test benches to block IP/subsystem/ SoC level verification and develop functional tests.
- Debug, rootcause and resolve functional failures in the design, partnering with the Design team.
- Collaborate with crossfunctional teams like Design, Architecture/Modeling, Emulation and Silicon validation teams towards ensuring the highest design quality.
Minimum Qualifications
- Requires a Master's degree (or foreign degree equivalent) in Electrical Engineering, Computer Engineering, Computer Science, Electrical and Computer Engineering, Electronics and Telecommunication Engineering or related field and 2 years of work experience in the job offered or related occupation. Requires 2 years of experience in the following skills:
- Verilog, System Verilog/UVM methodology based verification
- Block/IP/sub-system and/or SoC level verification based on System Verilog UVM based methodologies
- EDA tools and scripting (Python, Shell) used to build tools and flows for verification environments
- Implementing Design Verification infrastructure (Testbench, Functional coverage, Regression setup)
- Developing and executing verification test plans, random stimulus, coverage, and assertions
- Experience in debugging and root cause failures and tracking verification completion using metrics
- Experience working in a CPU or GPU or HW Accelerator verification
- Experience in executing a full verification cycle
$149,000/year to $162,580/year + bonus + equity + benefits
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