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Description
Develop MAC layer design for wireless communication SoCs, including creating microarchitecture and other documents based on system-level requirements, and writing area- and power-efficient RTL that is scalable. Work with systems and software teams to ensure performance and power efficiency. Collaborate with verification and emulation teams on debug, test plan review and code coverage closure. Run tools to ensure lint and CDC/RDC clean design. Work with synthesis team to review constraints, close timing and review area/timing reports.
Minimum Qualifications
BS in Electrical Engineering, Computer Engineering, or a related field, and 10+ years of relevant industry experience. Digital logic design fundamentals. Demonstrated experience in translating functional requirements into synthesizable Verilog or SystemVerilog RTL. Knowledge of digital design flows such as RTL simulation and debug, synthesis, lint, STA, and LEC. Ability to design multi-clock-domain logic and resolve CDC problems.
Preferred Qualifications
10+ years of experience in ASIC microarchitecture and RTL design. Excellent organization skills. Excellent communication skills – both written and oral. Understanding wireless standards, such as IEEE 802.11, 802.15, Bluetooth or 3GPP. Understanding of ASIC low power design techniques, e.g. multiple supply domains configuration and management, dynamic power/clock scaling and power analysis is a plus.
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