Reality Labs focuses on delivering Meta's vision through AI-first wearables devices. The compute performance and power efficiency requirements require custom silicon. The Reality Labs wearables team is driving the state-of-the-art forward with highly integrated SoCs that leverage breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable our wearables products to blend real and virtual worlds throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms. As a member of the SoC Subsystem Architecture team, you will play a key role in power architecture and modeling. You will analyze key workloads (graphics rendering, display, audio, computer vision, or color imaging) and collaborate with IP architects and execution engineers to architect subsystems that are software-usable, performant and power efficient. You will also act as a key point-of-contact representing the team with varying internal and external partners in a highly cross-functional environment, owning architectural models for workloads that run on custom silicon platforms.

Responsibilities

Lead technical analysis and optimization efforts for SOC subsystem design elements, utilizing data from simulation and hardware validation platforms
Develop Proof of Concept and Demo platforms to shift-left use-case bring-up, silicon system architecture analysis and pinpoint bottlenecks
Conduct analysis and optimization of SOC subsystems to achieve optimal power, performance, and area (PPA) targets
Drive architectural analysis for current and future workloads to inform SOC subsystem design decisions and roadmap planning
Collaborate with cross-functional teams to deliver technical documentation, architectural specifications, and performance models for SOC implementations

Minimum Qualifications

Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta
2+ years of experience with bare-metal programming, embedded FW, micro-benchmarking across pre and post silicon
Experience in creating prototypes and proof of concept for demos
Experience with post-silicon to pre-silicon power and performance correlation and trace analysis
Experience with developing and utilizing telemetry solutions to analyze and profile workloads
Knowledgeable in SoC system design principles and evaluating architectural trade-offs across key performance metrics including power, performance and area
Knowledgeable in low power architecture principles

Preferred Qualifications

Experience in at least one relevant area: Camera Sensors, Audio, Display, Rendering, Computer Vision, or Imaging
Experience performing workload analysis for power across a range of relevant workloads, including next-generation applications
Experience leading the analysis and configuration of subsystem memory hierarchy for optimal PPA
Experience deconstructing a problem, designing performance experiments, analyzing and visualizing data, and drawing conclusions for modeling and subsystem architecture
Demonstrated experience developing and maintaining power models for accelerator sub-systems
Experience collaborating with cross-functional partners to produce comprehensive documentation and modeling for workloads executed on accelerator sub-systems

$114,000/year to $172,000/year + bonus + equity + benefits

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