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Description
As part of the Pixel IP ANE design and integration engineer in pixel IP team, you will work closely with different cross functional team, including architecture, verification, power, physical design and more. Extensive knowledge of computer architecture is required, including bus topologies and protocols, such as AMBA. This role includes the following tasks: - Doing RTL design on high speed, high performance subsystem. - Working with design verification and formal verification teams to fully verify design and performance - Working with physical design and static timing team to produce high quality netlist through synthesis. - Analyze clock domain crossing design for correctness - Working with DFT, and BIST team to ensure design can be fully tested.
Minimum Qualifications
BS + 3 years of experience
Preferred Qualifications
Extensive knowledge of bus topology, such as AMBA is required. Experience working on large, high speed, compute system Good knowledge base on Clock Domain Crossing designs Experience with Synthesis Experience with Static Timing Analysis Experience working with Power Intent
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