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Description
As an ASIC Design Engineer in the Pixel IP design team, you will work closely with architecture, design, and verification teams to design high performance and low power pixel processing engines. Apply your knowledge of computer architecture and digital design to create digital signal processing pipelines for capturing, improving, compressing, decompressing, and displaying digital still images and video. In this front-end design role, your tasks will include: • Design digital hardware by writing high-quality RTL or using a high-level synthesis methodology, with embedded assertions and cover points. • Writing detailed micro-architectural specifications. • Collaborating with cross-functional teams to explore solutions that maximize performance while minimizing power and area. • Synthesizing your design and optimize for power, timing, and area. • Working closely with design verification and formal verification teams to debug and verify functionality and performance.
Minimum Qualifications
Bachelors Degree in EE/CE and 5+ years of relevant industry experience.
Preferred Qualifications
Experience in SoC front-end ASIC RTL digital logic design using Verilog or System Verilog. Prefer previous experience in media, video, pixel, or display designs. Experience working cross-functionally with architecture, design, and verification teams to specify, design, and debug designs. Good collaboration skills with strong written and verbal communication skills. Familiarity with low-power design techniques such as clock- and power-gating is a plus. Prefer familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB). Experience in front-end implementation tasks such as synthesis, timing, area/power analysis, linting, CDC/RDC, logic equivalence checks. Industry exposure to and knowledge of ASIC/FPGA design methodology including familiarity with relevant scripting languages (Python, Perl, TCL).
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