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Description
As a Pixel IP DMA Design Engineer in the Pixel IP team, you will work closely with architecture, design, and verification teams to build high performance and low power DMA engines that coordinate moving large amounts of data between the memory system and the Pixel IP Engine. In this front-end design role, your tasks will include: - Exploring solutions to enhance performance while minimizing power and area - Detailing specifications and building RTL designs - Working with design verification and formal verification teams to verify functionality and performance
Minimum Qualifications
Bachelors Degree + 10 years of experience
Preferred Qualifications
Experience in multimedia IP/SoC front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal communication skills Experience working multi-functionally with architecture, design, and verification teams to specify, design, and debug designs Previous experience designing dedication DMA engines (especially related to machine learning applications), data storage, memory controllers, networking, image processing, and/or interconnects Good understanding of arbitration, address translation, caching, on-chip interconnects, and performance analysis Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB) Experience in front-end implementation tasks such as synthesis, area and power analysis, linting, and logic equivalence checks
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