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Responsibilities
- Contribute to ASIC digital µArchitecture and design
- Assist performance/power analysis of the design and help meet power and performance targets
- Work with architects to map algorithms onto the hardware and specify requirements for IP and subsystems integration
- Collaborate with adjacent teams such as Verification, Physical Design, and Design-for-Test
- Develop micro-architecture, RTL coding, and design verification for complex IPs
- Drive IP/sub-system micro-architecture and RTL design in collaboration with DV and PD leads
Minimum Qualifications
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
- 6+ years of experience as a Hardware Design Engineer for production silicon shipped in volume
- Experience in digital design µArchitecture, RTL coding, and micro-architecture development
- Experience communicating technical design decisions and trade-offs to cross-functional partners such as verification, physical design, and architecture teams
Preferred Qualifications
- Experience in ML accelerator subsystems and top level design
- Experience in SoC integration and ASIC architecture
- Knowledge of microcontrollers, DSP, CDC and power sequence
- Demonstrated ability to integrate AI tools to optimize/redesign workflows and drive measurable impact (e.g., efficiency gains, quality improvements)
- Experience adhering to and implementing responsible, ethical AI practices (e.g., risk assessment, bias mitigation, quality and accuracy reviews)
- Demonstrated ongoing AI skill development (e.g., prompt/context engineering, agent orchestration) and staying current with emerging AI technologies
$146,000/year to $209,000/year + bonus + equity + benefits
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