Description
You will have the responsibilities as follows: Architect complex digital IP’s, meeting schedule, area, power, and performance targets. Provide guidance and focus on our internal Digital IP alignment and unification - Collaborate in developing precise design specifications for digital control blocks. - Collaborate with project System teams, CoreOS and Platform Architecture to provide the best guidance on PMU digital IP unified architecture - Work with DV teams to create verification plans and debug test failures. - Work with silicon validation team in developing lab validation and qualification plans.
Minimum Qualifications
BS and a minimum of 10 years relevant industry experience
Preferred Qualifications
10+ years of experience architecting digital IP’s for SoC’s or mixed signal IC’s. Proven track record of delivering quality designs on schedule. Experience with working closely with System partners, CoreOS. Solid understanding of low power design techniques.
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